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integrated circuit systems, inc. general description features ics9248-39 block diagram pentium is a trademark of intel corporation i 2 c is a trademark of philips corporation frequency generator & integrated buffers for pentium/pro tm 9248-39 rev f 12/16/99 pin configuration 3.3v outputs: sdram, pci, ref, 48/24mhz 2.5v outputs: cpu, ioapic 20 ohm cpu clock output impedance 20 ohm pci clock output impedance skew from cpu (earlier) to pci clock - 1.5 to 4 ns, center 2.6 ns. no external load cap for c l =18pf crystals 175 ps cpu clock skew 250ps (cycle to cycle) cpu jitter smooth frequency switch, with selections from 66.8 to 150 mhz cpu. i 2 c interface for programming 3ms power up clock stable time clock duty cycle 45-55%. 48 pin 300 mil ssop package 3.3v operation, 5v tolerant inputs (with series r) <5ns propagation delay sdram from buffer input 48-pin ssop power groups vdd1 = ref (0:1), x1, x2 vdd2 = pciclk_f, pciclk(0:4) vdd3 = sdram (0:12), supply for pll core vdd4 = 24mhz, 48mhz vddl1 = ioapic vddl2 = cpuclk 1, cpuclk_f * internal pull-up resistor of 240k to vdd ** internal pull-down resistor of 240k to gnd the ics9248-39 generates all clocks required for high speed risc or cisc microprocessor systems such as intel pentiumpro or cyrix. eight different reference frequency multiplying factors are externally selectable with smooth frequency transitions. features include two cpu, six pci and thirteen sdram clocks. two reference outputs are available equal to the crystal frequency. plus the ioapic output powered by vddl1. one 48 mhz for usb, and one 24 mhz clock for super io. spread spectrum built in at 0.5% or 0.25% modulation to reduce the emi. serial programming i 2 c interface allows changing functions, stop clock programing and frequency selection. additionally, the device meets the pentium power-up stabilization, which requires that cpu and pci clocks be stable within 2ms after power-up. it is not recommended to use i/o dual function pin for the slots (isa, pic, cpu, dimm). the add on card might have a pull up or pull down. high drive pciclk and sdram outputs typically provide greater than 1 v/ns slew rate into 30pf loads. cpuclk outputs typically provide better than 1v/ns slew rate into 20pf loads while maintaining 505% duty cycle. the ref and 24 and 48 mhz clock outputs typically provide better than 0.5v/ ns slew rates into 20pf. ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ics9248-39 pin descriptions notes: 1: internal pull-up resistor of 240k to 3.3v on indicated inputs 2: bidirectional input/output pins, input logic levels are latched at internal power-on-reset. use 10kohm resistor to program logic hi to vdd or gnd for logic low. r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 11 d d vr w pv 3 . 3 l a n i m o n , y l p p u s r e w o p l a t x , ) 2 : 0 ( f e r 2 0 f e rt u o r e g n o r t s e h t s i t u p t u o f e r s i h t . k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 s d a o l s u b a s i r o f r e f f u b # p o t s _ i c p 1 n i n i ( w o l t u p n i n e h w , l e v e l 0 c i g o l t a s k c o l c ) 4 : 0 ( k l c i c p s t l a h ) 0 = e d o m , e d o m e l i b o m , 2 2 , 6 1 , 9 , 3 5 4 , 9 3 , 3 3 d n gr w pd n u o r g 41 xn i k c a b d e e f d n a ) f p 6 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c 2 x m o r f r o t s i s e r 52 xt u o d a o l l a n r e t n i s a h . z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c ) f p 6 3 ( p a c 4 1 , 62 d d vr w pv 3 . 3 l a n i m o n , ) 4 : 0 ( k l c i c p d n a f _ k l c i c p r o f y l p p u s 7 f _ k l c i c pt u o r e w o p r o f # p o t s _ i c p y b d e t c e f f a t o n k c o l c i c p g n i n n u r e e r f . t n e m e g a n a m e d o m 2 , 1 n i . e d o m e l i b o m = 0 , e d o m p o t k s e d = 1 , n i p t c e l e s n o i t c n u f 2 n i p . t u p n i d e h c t a l 8 3 s fn id n g o t n w o d - l l u p l a n r e t n i . t u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 0 k l c i c pt u o w e k s s n 8 4 - 1 h t i w s k c o l c u p c o t s u o n o r e h c n y s . s t u p t u o k c o l c i c p ) y l r a e u p c ( 3 1 , 2 1 , 1 1 , 0 1) 4 : 1 ( k l c i c pt u o w e k s s n 8 4 - 1 h t i w s k c o l c u p c o t s u o n o r e h c n y s . s t u p t u o k c o l c i c p ) y l r a e u p c ( 5 1n i r e f f u bn i. s t u p t u o m a r d s r o f s r e f f u b t u o n a f o t t u p n i , 1 2 , 0 2 , 8 1 , 7 1 , 2 3 , 1 3 , 9 2 , 8 2 8 3 , 7 3 , 5 3 , 4 3 ) 0 : 1 1 ( m a r d st u o n i p n i r e f f u b m o r f s t u p t u o r e f f u b t u o n a f , s t u p t u o k c o l c m a r d s . ) t e s p i h c y b d e l l o r t n o c ( 6 3 , 0 3 , 9 13 d d vr w p. v 3 . 3 l a n i m o n , e r o c l l p u p c d n a ) 2 1 : 0 ( m a r d s r o f y l p p u s 3 2a t a d sn ii r o f t u p n i a t a d 2 t u p n i t n a r e l o t v 5 , t u p n i l a i r e s c 4 2k l c sn ii f o t u p n i k c o l c 2 t u p n i t n a r e l o t v 5 , t u p n i c 5 2 z h m 4 2t u ok c o l c t u p t u o z h m 4 2 1 s f 2 , 1 n i. t u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 6 2 z h m 8 4t u ok c o l c t u p t u o z h m 8 4 0 s f 2 , 1 n it u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 7 24 d d vr w p. e r o c l l p d e x i f d n a s r e f f u b t u p t u o z h m 8 4 & 4 2 r o f r e w o p 0 4f _ m a r d st u o# p o t s _ u p c y b d e t c e f f a t o n . t u p t u o k c o l c m a r d s g n i n n u r e e r f 1 4# p o t s _ u p cn i m a r d s & c i p a o i , 1 k l c u p c s t l a h t u p n i s u o n o r h c n y s a s i h t . w o l n e v i r d n e h w l e v e l " 0 " c i g o l t a ) 1 1 : 0 ( 2 42 l d d vr w pl a n i m o n v 3 . 3 r o v 5 . 2 r e h t i e , s k c o l c u p c r o f y l p p u s 3 41 k l c u p ct u ow o l = # p o t s _ u p c f i w o l . 2 l d d v y b d e r e w o p , s t u p t u o k c o l c u p c 4 4f _ k l c u p ct u o# p o t s _ u p c e h t y b d e t c e f f a t o n . k c o l c u p c g n i n n u r e e r f 6 4 1 f e rt u o. k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 2 s f 2 , 1 n it u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 7 4c i p a o it u oc i p a o i. 1 l d d v y b d e r e w o p z h m 8 1 3 . 4 1 . t u p t u o k c o l c 8 41 l d d vr w pl a n i m o n v 3 . 3 r o 5 . 2 r e h t i e , c i p a o i r o f y l p p u s
3 ics9248-39 functionality v dd 1,2,3 = 3.3v5%, v ddl 1,2 = 2.5v5% or 3.35%, ta=0 to 70c crystal (x1, x2) = 14.31818mhz mode pin - power management input control 7 n i p , e d o m ) t u p n i d e h c t a l ( 2 n i p 0 # p o t s _ i c p ) t u p n i ( 1 0 f e r ) t u p t u o ( 3 s f2 s f1 s f0 s f u p c ) z h m ( ) z h m ( k l c i c p 1111 3 3 1) 4 / u p c ( 3 . 3 3 1110 4 2 1) 4 / u p c ( 1 3 1101 0 5 1) 4 / u p c ( 5 . 7 3 1100 0 4 1) 4 / u p c ( 5 3 10 11 5 0 1) 3 / u p c ( 5 3 10 10 0 1 1) 3 / u p c ( 7 6 . 6 3 100 1 5 1 1) 3 / u p c ( 3 3 . 8 3 1000 0 2 1) 3 / u p c ( 0 0 . 0 4 0111 3 . 0 0 1) 3 / u p c ( 3 4 . 3 3 0110 3 3 1) 3 / u p c ( 3 3 . 4 4 0101 2 1 1) 3 / u p c ( 3 3 . 7 3 0100 3 0 1) 2 / u p c ( 3 3 . 4 3 0011 8 . 6 6) 2 / u p c ( 0 4 . 3 3 0010 3 . 3 8) 2 / u p c ( 5 6 . 1 4 0001 5 7) 2 / u p c ( 5 . 7 3 0000 4 2 1) 3 / u p c ( 3 3 . 1 4
4 ics9248-39 t i bn o i t p i r c s e dd w p 7 t i b n o i t a l u d o m m u r t c e p s d a e r p s % 5 2 . 0 - 0 n o i t a l u d o m m u r t c e p s d a e r p s % 5 . 0 - 1 0 4 t i b 5 t i b 6 t i b 2 t i bk c o l c u p ci c p 1 e t o n , 2 t i b 4 : 6 t i b 1 1 1 0 0 1 1 0 3 . 0 0 1 3 3 1 ) 3 / u p c ( 3 4 . 3 3 ) 3 / u p c ( 3 3 . 4 4 1 0 1 0 0 0 1 0 2 1 1 3 0 1 ) 3 / u p c ( 3 3 . 7 3 ) 3 / u p c ( 3 . 4 3 1 1 0 0 0 1 0 0 8 . 6 6 3 . 3 8 ) 2 / u p c ( 4 . 3 3 ) 2 / u p c ( 5 6 . 1 4 1 0 0 0 0 0 0 0 5 7 4 2 1 ) 2 / u p c ( 5 . 7 3 ) 3 / u p c ( 3 3 . 1 4 1 1 1 1 0 1 1 1 3 3 1 4 2 1 ) 4 / u p c ( 5 2 . 3 3 ) 4 / u p c ( 0 0 . 1 3 1 0 1 1 0 0 1 1 0 5 1 0 4 1 ) 4 / u p c ( 0 5 . 7 3 ) 4 / u p c ( 0 0 . 5 3 1 1 0 1 0 1 0 1 5 0 1 0 1 1 ) 3 / u p c ( 0 0 . 5 3 ) 3 / u p c ( 7 6 . 6 3 1 0 0 1 0 0 0 1 5 1 1 0 2 1 ) 3 / u p c ( 3 3 . 8 3 ) 3 / u p c ( 0 0 . 0 4 3 t i b s t u p n i d e h c t a l , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r f - 0 ) e v o b a ( 4 : 6 t i b y b d e t c e l e s s i y c n e u q e r f - 1 0 1 t i b l a m r o n - 0 ) d a e r p s r e t n e c ( d e l b a n e m u r t c e p s d a e r p s - 1 0 0 t i b g n i n n u r - 0 s t u p t u o l l a e t a t s i r t - 1 0 byte0: functionality and frequency select register (default = 0) serial configuration command bitmap note: pwd = power-up default note 1. default at power-up will be for latched logic inputs to define frequency. bits 4, 5, 6 are default to 000, and if bit 3 is written to a 1 to use bits 6:4, then these should be defined to desired frequency at same write cycle.
5 ics9248-39 notes: 1. inactive means outputs are held low and are disabled from switching. 2. latched frequency selects (fs#) will be inverted logic load of the input frequency select pin conditions. byte 2: pci active/inactive register (1 = enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b71 ) t c a n i / t c a ( f _ k l c i c p 5 t i b-1 ) d e v r e s e r ( 4 t i b3 11 ) t c a n i / t c a ( 4 k l c i c p 3 t i b2 11 ) t c a n i / t c a ( 3 k l c i c p 2 t i b1 11 ) t c a n i / t c a ( 2 k l c i c p 1 t i b0 11 ) t c a n i / t c a ( 1 k l c i c p 0 t i b81 ) t c a n i / t c a ( 0 k l c i c p byte 1: cpu, active/inactive register (1 = enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-x # 2 s f d e h c t a l 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b-1 ) d e v r e s e r ( 3 t i b0 41 ) t c a n i / t c a ( 2 1 m a r d s 2 t i b-1 ) d e v r e s e r ( 1 t i b3 41 ) t c a n i / t c a ( 1 k l c u p c 0 t i b4 41 ) t c a n i / t c a ( f _ k l c u p c byte 3: sdram active/inactive register (1 = enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-x # 0 s f d e h c t a l 5 t i b6 21 ) t c a n i / t c a ( z h m 8 4 4 t i b5 21 ) t c a n i / t c a ( z h m 4 2 3 t i b-1 ) d e v r e s e r ( 2 t i b7 1 , 8 1 , 0 2 , 1 21 ) e v i t c a n i / e v i t c a ( ) 1 1 : 8 ( m a r d s 1 t i b8 2 , 9 2 , 1 3 , 2 31 ) e v i t c a n i / e v i t c a ( ) 7 : 4 ( m a r d s 0 t i b4 3 , 5 3 , 7 3 , 8 31 ) e v i t c a n i / e v i t c a ( ) 3 : 0 ( m a r d s
6 ics9248-39 byte 4: reserved active/inactive register (1 = enable, 0 = disable) byte 5: peripheral active/inactive register (1 = enable, 0 = disable) notes: 1. inactive means outputs are held low and are disabled from switching. 2. latched frequency selects (fs#) will be inverted logic load of the input frequency select pin conditions. t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b-1 ) d e v r e s e r ( 3 t i b-x # 1 s f d e h c t a l 2 t i b-1 ) d e v r e s e r ( 1 t i b-x # 3 s f d e h c t a l 0 t i b-1 ) d e v r e s e r ( t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b7 41 ) t c a n i / t c a ( 0 c i p a o i 3 t i b-1 ) d e v r e s e r ( 2 t i b-1 ) d e v r e s e r ( 1 t i b6 41 ) t c a n i / t c a ( 1 f e r 0 t i b21 ) t c a n i / t c a ( 0 f e r
7 ics9248-39 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c case temperature . . . . . . . . . . . . . . . . . . . . . . . . 115c storage temperature . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operation al sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70o c; supply voltage v dd, v ddl = 3.3 v +/-5% (unless otherwise stated) parameter symbol c onditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 0.1 5 a input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 2.0 a input low current i il2 v in = 0 v; inputs with pull-up resistors -200 -100 a operating i dd3.3op66 c l = 0 pf; select @ 66mhz 146 supply current i dd3.3op100 c l = 0 pf; select @ 100mhz 174 input frequency f i v dd = 3.3 v; 12 14.318 16 mhz input capacitance 1 c in logic inputs 5 pf c inx x1 & x2 pins 27 36 45 pf clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3ms 1 guaranteed by design, not 100% tested in production. ma 180 electrical characteristics - input/supply/common output parameters t a = 0 - 70o c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units operating i dd2.5op66 c l = 0 pf; select @ 66.8 mhz 4 72 supply current i dd2.5op100 c l = 0 pf; select @ 100 mhz 6 100 skew1 t cp u-p ci v t = 1.5 v; v tl = 1.25 v 1.5 2.5 4 ns 1 guaranteed by design, not 100% tested in production. ma
8 ics9248-39 electrical characteristics - cpuclk t a = 0 - 70o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh2 b i oh = -12.0 ma 2 2.23 v output low voltage v ol2 b i ol = 12 ma 0.32 0.4 v output high current i oh2 b v oh = 1.7 v -32 -19 ma output low current i ol2 b v ol = 0.7 v 19 25 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 1.48 1.6 ns fall time t f2b 1 v oh = 2.0 v, v ol = 0.4 v 1.25 1.6 ns duty cycle d t2b 1 v t = 1.25 v 454555% skew t sk2b 1 v t = 1.25 v 125 175 ps jitter, cycle-to-cycle t jcyc-cyc2b 1 v t = 1.25 v 225 250 ps jitter, one sigma t j1s2b 1 v t = 1.25 v 36 150 ps jitter, absolute t jabs2b 1 v t = 1.25 v -250 130 +250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - pciclk t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh1 i oh = -11 ma 2.4 3.05 v output low voltage v ol1 i ol = 9.4 ma 0.17 0.4 v output high current i oh1 v oh = 2.0 v -52 -22 ma output low current i ol1 v ol = 0.8 v 25 40 ma ris e time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 2 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 1.65 2 ns duty cycle 1 d t1 v t = 1.5 v 45 49 55 % skew 1 t sk1 v t = 1.5 v 240 500 ps jitter, cycle-to-cycle t jcyc-cyc2b 1 v t = 1.5 v 210 250 ps jitter, one sigma 1 t j1s1 v t = 1.5 v 18 150 ps jitter, absolute 1 t jabs1 v t = 1.5 v -500 90 500 ps 1 guaranteed by design, not 100% tested in production.
9 ics9248-39 electrical characteristics - sdram t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh3 i oh = -28 ma 2.4 2.9 v output low voltage v ol3 i ol = 23 ma 0.4 0.4 v output high current i oh3 v oh = 2.0 v -77 -54 ma output low current i ol3 v ol = 0.8 v 41 41 ma rise time t r3 1 v ol = 0.4 v, v oh = 2.4 v 1.5 2 ns fall time t f3 1 v oh = 2.4 v, v ol = 0.4 v 1.8 2 ns duty cycle d t3 1 v t = 1.5 v 45 49.5 55 % skew 1 t sk1 v t = 1.5 v 190 500 ps propagation delay tprop vt = 1.5 v 3 5 ns 1 guarenteed by design, not 100% tested in production. electrical characteristics - ioapic t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh4b i oh = -12 ma 2 2.12 v output low voltage v ol4b i ol = 12 ma 0.32 0.4 v output high current i oh4b v oh = 1.7 v -23 -19 ma output low current i ol4b v ol = 0.7 v 19 25 ma ris e time 1 t r4b v ol = 0.4 v, v oh = 2.0 v 1.45 2 ns fall time 1 t f4 b v oh = 2.0 v, v ol = 0.4 v 1.3 2 ns duty cycle 1 d t4b v t = 1.25 v 45 51 55 % jitter, one sigma 1 t j1s4b v t = 1.25 v 0.2 0.5 ns jitter, absolute 1 t jabs4b v t = 1.25 v -1 0.5 1 ns 1 guaranteed by design, not 100% tested in production.
10 ics9248-39 electrical characteristics - 24mhz, 48mhz, ref(0:1) t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -16 ma 2.4 2.73 v output low voltage v ol5 i ol = 9 ma 0.23 0.4 v output high current i oh5 v oh = 2.0 v -32 -22 ma output low current i ol5 v ol = 0.8 v 16 28 ma ris e time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 1.8 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 1.8 4 ns duty cycle 1 d t5 v t = 1.5 v 45 51 55 % jitter, one sigma 1 t j1s5 v t = 1.5 v 0.2 0.5 ns jitter, absolute 1 t jabs5 v t = 1.5 v -1 0.5 1 ns 1 guaranteed by design, not 100% tested in production.
11 ics9248-39 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends a dummy command code ics clock will acknowledge controller (host) sends a dummy byte count ics clock will acknowledge controller (host) starts sending first byte (byte 0) through byte 5 ics clock will acknowledge each byte one at a time . controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the byte count controller (host) acknowledges ics clock sends first byte (byte 0) through byte 5 controller (host) will need to acknowledge each byte controller (host) will send a stop bit notes: controller (host) ics (slave/receiver) start bit address d3 (h) a ck byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) a ck dummy command code a ck dummy byte count a ck byte 0 a ck byte 1 ack byte 2 a ck byte 3 a ck byte 4 a ck byte 5 a ck stop bit how to write:
12 ics9248-39 cpu_stop# timing diagram cpu_stop# is an asychronous input to the clock synthesizer. it is used to turn off the cpu clocks for low power operation. cpu_stop# is synchronized by the ics9248-39 . the minimum that the cpu clock is enabled (cpu_stop# high pulse) is 100 cpu clocks. all other clocks will continue to run while the cpu clocks are disabled. the cpu clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. cpu clock on latency is less th an 4 cpu clocks and cpu clock off latency is less than 4 cpu clocks. notes: 1. all timing is referenced to the internal cpu clock. 2. cpu_stop# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpu clocks inside the ics9248-39. 3. ioapic output is stopped glitch free by cpustop# going low. 4. sdram-f output is controlled by buffer in signal, not affected by the ics9248-39 cpu_stop# signal. sdram (0:11) are controlled as shown. 5. all other clocks continue to run undisturbed.
13 ics9248-39 pci_stop# timing diagram pci_stop# is an asynchronous input to the ics9248-39 . it is used to turn off the pciclk (0:4) clocks for low power operation. pci_stop# is synchronized by the ics9248-39 internally. the minimum that the pciclk (0:4) clocks are enabled (pci_stop# high pulse) is at least 10 pciclk (0:4) clocks. pciclk (0:4) clocks are stopped in a low state and started with a full high pulse width guaranteed. pciclk (0:4) clock on latency cycles are only one rising pciclk clock off latency is one pciclk clock. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9248 device.) 2. pci_stop# is an asynchronous input, and metastable conditions may exist. this signal is required to be synchronized inside the ics9248. 3. all other clocks continue to run undisturbed. 4. cpu_stop# is shown in a high (true) state.
14 ics9248-39 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) on the ics9248- 39 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
15 ics9248-39 general layout precautions: 1) use a ground plane on the top layer of the pcb in all areas not used by traces. 2) make all power traces and vias as wide as possible to lower inductance. notes: 1 all clock outputs should have series terminating resistor. not shown in all places to improve readibility of diagram 2 optional emi capacitor should be used on all cpu, sdram, and pci outputs. 3 optional crystal load capacitors are recommended. capacitor values: c1, c2 : crystal load values determined by user c3 : 100pf ceramic all unmarked capacitors are 0.01f ceramic
16 ics9248-39 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ordering information ics9248 y f-39 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y f - ppp .093 dia. pin (optional) d/2 e/2 bottom view a 1 -e- b a side view -c- -d- seating plane a 2 see detail ?a? -e- c end view parting line l detail ?a? h pin 1 top view index area l o b m y ss n o i s n e m i d n o m m o cs n o i t a i r a vdn . n i m. m o n. x a m. n i m. m o n. x a m a5 9 0 .2 0 1 .0 1 1 .c a0 2 6 .5 2 6 .0 3 6 .8 4 1 a8 0 0 .2 1 0 .6 1 0 . 2 a7 8 0 .0 9 0 .4 9 0 . b8 0 0 .- 5 3 1 0 . c5 0 0 .- 5 8 0 0 . ds n o i t a i r a v e e s e1 9 2 .5 9 2 .9 9 2 . ec s b 5 2 0 . 0 h5 9 3 .-0 2 4 . h0 1 0 .3 1 0 .6 1 0 . l0 2 0 .-0 4 0 . ns n o i t a i r a v e e s 0- 8 48 pin 300 mil ssop package ?for current dimensional specifications, see jedec 95.?
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